Adders

 Half Adder

 Combinational logic circuit with two inputs and two outputs. 

The half adder circuit is designed to add two single bit binary number A and B. 

It is the basic building block for addition of two single bit numbers. 

It has two outputs carry and sum.

Circuit of Half Adder

Truth Table of Half Adder

A	B	S	C
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

first 

0+0 = 0

second

0+1 = 1

Third 

1+0 = 1

Forth

1+1 = 10

These are the least possible single-bit combinations. But the result for 1+1 is 10, the sum result must be re-written as a 2-bit output. Thus, the equations can be written as

0+0 = 0 0
0+1 = 0 1
1+0 = 0 1
1+1 = 1 0

Carry Bit        Sum

0                     0

0                     1

0                     1

1                     0

Karnaugh Map for Carry Bit

 

Result

 

Simulate the circuit with using XOR Gate

Circuit of Carry - C

Karnaugh Map of Carry - C

F = AB

Both Gates in Together

Simulate with Logisim

Full Adder

 

• It is used for the purpose of adding two single bit numbers with a carry.
• It has the ability to perform the addition of three bits.
• Full adder contains 3 inputs and 2 outputs (sum and carry)

Truth Table

Inputs			Outputs
A	B	Cin	Cout (Carry)	S (Sum)
0	0	0	0	0
0	0	1	0	1
0	1	0	0	1
0	1	1	1	0
1	0	0	0	1
1	0	1	1	0
1	1	0	1	0
1	1	1	1	1

 

First ,

       0 + 0 + 0 = 0  (Sum)

Second,

       0 + 0 + 1 = 1  (Sum)

Third ,

       0 + 1 + 0 = 1  (Sum)

Fourth ,

       0 + 1 + 1 = 1 (Carry Bit) 0  (Sum)

Fifth ,

       1 + 0 + 0 = 1  (Sum)

Sixth,

       1 + 0 + 1 =1(Carry Bit)  0  (Sum)

Seventh ,

       1 + 1 + 0 = 1(Carry Bit)  0  (Sum)

Eighth ,

       1 + 1 + 1 = 1(Carry Bit)  1  (Sum)

Karnaugh Map for Sum - S

           Circuit

Karnaugh Map for Carry - C out

Circuit of Full Adder

 

Simulate Circuit